Undergraduate Internship Programme
(Research project of up to six months duration)

For application forms, please click internship application here & TEP application here .

Suggested Project Titles and Descriptions:

Title: Efficient Techniques for Hardware/Software Partitioning
This project focuses on the partitioning and scheduling problems at a higher abstraction level-- the task or functional level. At this level the atomic partitioning and scheduling unit is a task.  The two problems are interdependent and both are optimization problem subject to the constraints in execution time, communication time, power, and hardware area. The corresponding techniques and approaches include heuristic strategy, branch-and-bound algorithm, dynamic programming approach, and so on.  The challenge of this project is to explore and design novel strategies. Approximation algorithms will be preferred due to the Np-hardness of the partitioning and scheduling problems. An important part of the project will be the experimentation to determine limits of the proposed algorithms.

Title: Using DTW to maintain sequence information in a GMM

The program objective is to look for a robust model for limited vocabulary speech recognition that is less computationally intensive than the Hidden Markov Model (HMM). While HMM has been shown to be a reliable statistical model for speech feature vectors, the procedure for modeling and matching requires significant computing resources. Therefore, from an embedded systems perspective, it is desirable to have a simpler model for speech recognition.
Title: 3-D Rendering on Soft-core Processor

This project aims at developing 3D rendering on softcore processor using techniques like hardware software partitioning and profiling. A high performance and compact solution is envisaged to be designed and developed for a 3D rendering application.
Title: FPGA Implementation of GMM-based Speaker-Aware Isolated Word Recognition

There are several emerging applications that require speaker-aware isolated word recognition to be performed in real-time or faster than real-time.  Software versions of today’s state-of-the-art recognizers are incapable of providing the multiple orders-of-magnitude speedups required by such applications.  It is envisaged that a hardware accelerator based on the Gaussian Mixture Model  (GMM) framework has the potential to achieve the desired performance .  This project will examine all issues and trade-offs involved in the algorithm-to-architecture mapping of GMM-based speaker-aware isolated word recognition.  Field Programmable Gate Array (FPGA) will be used as the platform for evaluating the effectiveness of the proposed approach.
Title: Simulation Model for Evaluating Traffic-Aware Routing in Transportation Networks

A scenario is envisaged where the route choices of motorists in a transportation network are influenced by the current and anticipated traffic conditions. The project involves the construction of a simulation platform that models a real urban road network  and its travel time trends. It should also be capable of modelling the effect of traffic incidents on the travel times of the links in the network. The simulation model would be used to evaluate alternative methods of incorporating the traffic information into the routing process and to empirically quantify the benefits in terms of travel-time savings over static routing solutions.
Title: Porting Micro T-Kernel to the TriCore

The µT-Kernel is an open source, real-time operating system (RTOS) specified for use in smaller deeply embedded systems (running 8- and 16-bit microcontrollers, although it can also be used on 32-bit microcontrollers). The µT-Kernel is standardized by T-Engine Forum and has an API that is compatible with the T-Kernel family.

This project aims to port the µT-Kernel and associated software stack to run on the TriCore TC116x or the TC1130 processors from Infineon. The TriCore CPU is a single core 32-bit MCU DSP architecture from Infineon, optimized for real-time embedded systems and combines the real-time capabilities of microcontrollers, computational power of DSPs, and the price/performance benefits of RISC load-store architectures.
Title: SDK for TriCore/T-Kernel Significant amount of work has been done at CHiPES to port the T-Engine software stack to the T-Kernel.This system uses the GNU compiler toolchain for building the RTOS stack, as well as applications to run on the RTOS. However, there is a need to customize and produce a software development kit (SDK) that can be used more effectively for developing different kinds of middleware (device drivers, subsystems, etc.) and applications for the T-Kernel stack running on the TriCore.

This project aims to produce the SDK for the TriCore/T-Kernel.The work involves the creation of necessary supporting libraries, support for different types of build environments, creation of necessary make files and headers for the different types of targets, and the customization of the standard libraries to make them compatible with the T-Kernel on the TriCore.
Title: Kernel Port to TC116x The T-Engine is an open platform for the development of real-time and embedded systems. It comprises a hardware and software platform standardized by the T-Engine Forum in Japan. The T-Kernel is the open-source operating system within the T-Engine software stack. It is evolved from ITRON, arguably the most embedded RTOS.
This project aims to port the T-Kernel and associated software stack to run on the TriCore TC116x processors from Infineon. The TC116x is a single core 32-bit MCU DSP architecture from Infineon, optimized for real-time embedded systems and combines the real-time capabilities of microcontrollers, computational power of DSPs, and the price/performance benefits of RISC load-store architectures.
Title: Power Management Subsystem for Infineon TriCore/T-Kernel

In modern embedded systems, management of energy and power consumption is critical.  Modern embedded processors, such as the Infineon TriCore offer numerous modes to reduce the power consumption of the system.  Further, input/ output peripherals can also be controlled to ensure system-optimal energy consumption.  To make effective use of the myriad power management features, suitable policies need to be developed and integrated at different layers in the software  stack of the embedded system.  This research project aims to develop application specific techniques to realize an RTOS based dynamic power management system. It is envisaged that application aware strategies for energy centric partitioning and management will lead to efficient DPM solutions for dedicated systems.  The dynamic power management subsystem and associated policies will be integrated into a system running the T-Engine software stack on the Infineon TriCore CPU.
Title: Safety subsystem for Infineon TriCore/T-Kernel

The power train is the system that generates the force needed to propel the vehicle and transmits this force to its proper destination.  Power train control includes engine and transmission control.  The flexibility of microprocessor-based power train control systems allows the designer to deal effectively with the relatively large number of system elements.  However, this same flexibility requires a system to ensure that major constraints are continually satisfied while still enforcing safety requirements. The TriCore family of microcontrollers from Infineon includes a number of architectural and on-chip features that provide good support for the implementation of safety and reliability features in a system.  The efficient us of these features requires that they presented to the system or application layer using a consistent API.  The T-Engine software stack does not directly have any specific features that support (or prevent) the implementation of safety features.  This project aims to develop such a subsystem for a system running the T-Engine software stack on the Infineon TriCore CPU.
Title: High-Level Area-Time Estimation of C-based Applications for FPGA Implementation

Combining reconfigurable hardware and microprocessors provide a promising solution to cater to the demands of future embedded systems. Rapid design exploration of these reconfigurable processors must be undertaken in order to identify a set of profitable hardware realizations for a given application. This necessitates efficient techniques that can rapidly estimate the hardware area-time costs of C-based applications without the need for time-consuming hardware implementation. This project aims to develop a high-level estimation technique that is based on a clustering strategy to efficiently map data-paths onto the FPGA (Field-Programmable Gate Array). The proposed technique should incorporate methods to predict the effects of logic optimizations that are commonly employed in commercial FPGA tools. In addition, the proposed technique must be capable of estimating IP cores required for implementing complex operations such as multiplication, division, etc. The effectiveness of the proposed approach in terms of accuracy, scalability and portability must be evaluated by comparing the estimated area-time measures with implementation results of existing FPGA tools.
Title: Mapping Area-Time Efficient Data-paths onto FPGAs

Area-time efficient realization of data-paths is desirable for maximizing the utilization of FPGAs (Field-Programmable Gate Arrays). Area-time optimizations can be performed at various level of design abstractions, e.g. during high-level or gate level synthesis. Since the designs at the higher level of abstractions is less confined to the physical architecture, optimizations at these levels usually lead to high quality results. This project aims to propose a strategy for mapping area-time efficient data-paths onto the reconfigurable space by taking into account the inherent architecture constraints of the FPGA. The scalability of the proposed method must be demonstrated by mapping data-paths from C functions with varying degree of complexity onto the FPGA architecture. In order to evaluate the effectiveness of the proposed technique, area-time results of the proposed technique must be compared with results of existing high-level optimization approaches.
Title: Framework for Dynamic Instruction Set Customization

Despite the active amount of instruction set customization related research activities that has taken place recently, there still exists a need for more effective solutions to meet the increasing challenges of embedded systems. Dynamic instruction set customization is capable of maximizing the benefits of a RISP (Reconfigurable Instruction Set Processor) with restricted reconfigurable resource area by catering to the application characteristics at runtime. An inherent problem in RISP arises from the reconfiguration overhead that is incurred while reusing the hardware resources for various functions. The aim of this project is to establish efficient dynamic reconfiguration strategies for implementing custom instructions on the RISP. Techniques for selecting the appropriate custom instructions and mapping them into appropriate configurations must be devised. The proposed strategies should focus on maximizing the utilization of a restricted FPGA space, while minimizing the dynamic reconfiguration overhead.
Title: Run-Time Reconfiguration Strategies for Instruction Set Customization

The need for customization and flexibility has led to the popularity of reconfigurable architectures such as the FPGA (Field-Programmable Gate Array). Run-time reconfiguration can further increase the cost efficiency of these architectures by means of hardware virtualization. Commercial FPGAs facilitate partial reconfiguration, which allows for run-time reconfiguration of a hardware region without affecting the execution of the remaining section. However, the lack of tools and architecture support discourages the adoption of run-time reconfiguration in realistic applications. In addition, the minimal reconfiguration time of commercial FPGAs is still in the order of milliseconds, which is unacceptable for most applications. It is envisioned that the run-time reconfigurable capability of commercial FPGAs can be enhanced through a framework that enables self-reconfiguration. The goal of this project is to develop an efficient framework for self-reconfiguration in commercial FPGAs. The proposed framework should incorporate lightweight modules that are embedded within the reconfigurable architecture to enable partial reconfiguration. The benefits of the proposed framework can be demonstrated through simulations using realistic examples.
Title: Accelerating Reconfiguration of Degradable VLSI Arrays

The mesh-connected VLSI array has a regular and modular structure and allows highly parallel computation of most signal and image processing algorithms. With the advancements in Wafer Scale Integration (WSI) technologies, mesh-connected processor arrays can now be integrated on a single chip. As the density of embedded accelerators consisting of WSI arrays increases, the probability of occurrence of defects also increases during fabrication process. In order to cater for dynamic faults due to harsh operating conditions, fault-tolerant techniques must be employed to improve reliability of WSI arrays. It is envisioned that a hardware accelerator that dynamically reconfigures the degradable VLSI array will increase the reliability of processor array based platforms that are targeted towards real-time and performance critical applications. This project aims to develop efficient hardware accelerators for dynamic reconfiguration of degradable VLSI arrays. State-of-the-art languages tools for hardware design such as VHDL and FPGA-based synthesis tools will be employed to realize the hardware accelerators for realistic area-time analysis.